 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| August 2000 AS7C513 AS7C3513 5V/3.3V 32Kx16 CMOS SRAM AS7C513 (5V version) AS7C3513 (3.3V version) Industrial and commercial temperature Organization: 32,768 words x 16 bits Center power and ground pins High speed - 12/15/20 ns address access time - 5/7/9 ns output enable access time * Low power consumption: ACTIVE - 800 mW (AS7C513) / max @ 12 ns - 432 mW (AS7C3513) / max @ 12 ns * * * * * * * Low power consumption: STANDBY - 28 mW (AS7C513) / max CMOS - 18 mW (AS7C3513) / max CMOS * 2.0V data retention * Easy memory expansion with CE, OE inputs * TTL-compatible, three-state I/O * 44-pin JEDEC standard package - 400 mil SOJ - 400 mil TSOP II * ESD protection 2000 volts * Latch-up current 200 mA A0 Row decoder A1 A2 A3 A4 A5 A6 A7 I/O0-I/O7 I/O8-I/O15 VCC 44-Pin SOJ, TSOP II (400 mil) NC A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A14 A13 A12 A11 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A4 A5 A6 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A7 A8 A9 A10 NC 32K x 16 Array GND Control circuit Column decoder A8 A9 A10 A11 A12 A13 A14 WE UB OE LB CE AS7C513-12 AS7C3513-12 Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current Shaded areas indicate advance information. AS7C513-15 AS7C3513-15 15 7 150 110 5 5 AS7C513 AS7C3513 I/O buffer AS7C513-20 AS7C3513-20 20 9 140 100 5 5 Unit ns ns mA mA mA mA 12 5 AS7C513 AS7C3513 AS7C513 AS7C3513 160 120 5 5 The AS7C513 and the AS7C3513 are high performance CMOS 524,288-bit Static Random Access Memory (SRAM) devices organized as 32,768 words x 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, t WC) of 12/15/20 ns with output enable access times (t OE) of 5/7/9 ns are ideal for high performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high, the devices enter standby mode. The AS7C513 and AS7C3513 are guaranteed not to exceed 28/18 mW power consumption in CMOS standby mode. The devices also offer 2.0V data retention. A write cycle is accomplished by asserting write enable (WE), (UB) and/or (LB), and chip enable (CE). Data on the input pins I/O0-I/O7, and/or I/O8-I/O15, is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), (UB) and (LB), and chip enable (CE), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, or (UB) and (LB), output drivers stay in high-impedance mode. The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0-I/O7, and UB controls the higher bits, I/O8-I/O15. All chip inputs and outputs are TTL-compatible. The AS7C513 and AS7C3513 are packaged in common industry standard packages. Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with V CC applied Device AS7C513 AS7C3513 Symbol Vt1 Vt1 Vt2 PD Tstg Tbias Min -0.50 -0.50 -0.50 - -65 -55 Max +7.0 +5.0 VCC +0.50 1.0 +150 +125 Unit V V V W o o C C DC current into outputs (low) IOUT - 50 mA NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CE H L L L L L L L L WE X H H H L L L H X OE X L L L X X X H X LB X L H L L L H X H UB X H L L L H L X H I/O0-I/O7 High Z DOUT High Z DOUT DIN DIN High Z High Z I/O8-I/O15 High Z High Z DOUT DOUT DIN High Z DIN High Z Mode Standby (ISB, ISBI) Read I/O0-I/O7 (I CC) Read I/O8-I/O15 (ICC) Read I/O0-I/O15 (ICC) Write I/O0-I/O15 (ICC) Write I/O0-I/O7 (ICC) Write I/O8-I/O15 (ICC) Output disable (ICC) Key: X = Don't care; L = Low; H = High Parameter Supply voltage Device AS7C513 AS7C3513 AS7C513 AS7C3513 commercial industrial Symbol VCC VCC VIH VIH VIL TA TA Min 4.5 3.0 2.2 2.0 -0.5 0 -40 Typical 5.0 3.3 - - - - - Max 5.5 3.6 VCC + 0.5 VCC + 0.5 0.8 70 05 Unit V V V V C C Input voltage Ambient operating temperature V IL min = -3.0V for pulse width less than t RC/2. -12 Parameter Input leakage current Output leakage current Symbol | ILI | | ILO | -15 -20 Test conditions VCC = Max VIN = GND to VCC VCC = Max VOUT = GND to VCC VCC = Max, CE VIL f = fMax , IOUT = 0mA VCC = Max, CE VIL f = fMax , IOUT = 0mA VCC = Max, CE VCC-0.2V VIN GND + 0.2V or VIN VCC -0.2V, f = 0 IOL = 8 mA, VCC = Min IOH = -4 mA, VCC = Min Device Min Max Min Max Min Max Unit - - 1 1 160 120 40 40 3 3 0.4 - - - - - - - - - - 2.4 1 1 150 110 40 40 3 3 0.4 - - - - - - - - - - 2.4 1 1 140 100 40 40 3 3 0.4 - mA V V A A mA mA Operating power supply ICC current ISB Standby power supply current ISB1 VOL VOH AS7C513 AS7C3513 AS7C513 AS7C3513 AS7C513 AS7C3513 - - - - - - - 2.4 Output voltage Shaded areas indicate advance information. Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE, WE, OE, LB, UB I/O Test conditions Vin = 0V Vin = Vout = 0V Max Unit 5 7 pF pF -12 Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change CE Low to output in low Z CE High to output in high Z OE Low to output in low Z Byte select access time Byte select Low to low Z Byte select High to high Z OE High to output in high Z Power up time Power down time Shaded areas indicate advance information. -15 Max - 12 12 5 - - 6 - 6 - 6 6 - 12 Min 15 - - - 4 0 - 0 - 0 - - 0 - Max - 15 15 7 - - 7 - 7 - 7 7 - 15 Min 20 - - - 4 0 - 0 - 0 - - 0 - -20 Max - 20 20 9 - - 8 - 9 - 9 9 - 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4,5 4,5 4, 5 4, 5 4, 5 5 4, 5 4, 5 4, 5 3 3 Notes Symbol tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tBA tBLZ tBHZ tOHZ tPU tPD Min 12 - - - 3 0 - 0 - 0 - - 0 - tRC Address tOH Data OUT Previous data valid tAA Data valid tOH tRC Address tAA OE tOE tOLZ CE tACE tLZ LB, UB tBLZ Data OUT tBA Data valid tBHZ tOHZ tHZ tOH -12 Parameter Write cycle time Chip enable (CE) to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Byte select Low to end of write Shaded areas indicate advance information. -15 Min 15 10 10 0 10 0 8 0 - 3 9 Max - - - - - - - - 7 - - - - - - - - - - 6 - - 20 12 12 0 12 0 10 0 - 3 12 -20 Min Max - - - - - - - - 9 - - Unit ns ns ns ns ns ns ns ns ns ns ns 5 4, 5 4, 5 Notes Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW tBW Min 12 9 8 0 8 0 6 0 - 3 8 Max tWC Address tBW LB, UB tAS WE tDW Data IN tWZ Data OUT Data undefined Data valid tOW High-Z tDH tAW tWP tWC Address tAS CE tCW tAW tBW LB, UB tWP WE tDW Data IN tCLZ Data OUT High-Z tWZ Data undefined High-Z Data valid tOW tDH tAH Parameter VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Input leakage current Symbol VDR ICCDR tCDR tR | ILI | Test conditions VCC = 2.0V CE VCC-0.2V VIN VCC-0.2V or VIN 0.2V Min 2.0 - 0 tRC - Max - 500 - - 1 Unit V A ns ns A Data retention mode VCC VCC tCDR CE VIH VDR VIH VDR 2.0V VCC tR - Output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 During V CC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, and C. These parameters are specified with C L = 5pF, as in Figures B or C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. 2V data retention applies to the commercial operating range only. C=30pF, except on High Z and Low Z parameters, where C=5pF. 1.4 1.2 Normalized ICC, ISB 1.0 0.8 0.6 0.4 0.2 Normalized supply current I CC, ISB vs. supply voltage VCC 1.4 1.2 Normalized ICC, ISB Normalized supply current ICC, ISB vs. ambient temperature Ta Normalized ISB1 (log scale) 625 25 5 1 0.2 Normalized supply current ISB1 vs. ambient temperature T a ICC 1.0 0.8 0.6 0.4 0.2 ICC VCC = VCC(NOMINAL) ISB ISB 0.04 -55 -10 35 80 125 Ambient temperature (C) 0.0 MIN NOMINAL Supply voltage (V) Normalized access time tAA vs. supply voltage VCC MAX 0.0 -55 -10 35 80 125 Ambient temperature (C) Normalized access time tAA vs. ambient temperature Ta 1.5 1.4 Normalized access time 1.3 1.2 1.1 1.0 0.9 0.8 MIN 1.5 1.4 Normalized access time 1.4 1.2 Normalized supply current I CC vs. cycle frequency 1/tRC, 1/t WC Ta = 25C 1.2 1.1 1.0 0.9 0.8 -55 -10 35 80 125 Ambient temperature (C) Output sink current I OL vs. output voltage VOL Normalized ICC 1.3 VCC = VCC(NOMINAL) 1.0 0.8 0.6 0.4 0.2 0.0 0 VCC = VCC(NOMINAL) Ta = 25C NOMINAL Supply voltage (V) Output source current IOH vs. output voltage VOH MAX 25 50 75 Cycle frequency (MHz) 100 Typical access time change tAA vs. output capacitive loading 35 30 Change in tAA (ns) VCC = VCC(NOMINAL) 140 Output source current (mA) 120 100 80 60 40 20 0 0 140 Output sink current (mA) 120 100 80 60 40 20 0 VCC 0 VCC = VCC(NOMINAL)PL Ta = 25C VCC = VCC(NOMINAL) Ta = 25C 25 20 15 10 5 0 VCC Output voltage (V) 0 Output voltage (V) 250 500 750 Capacitance (pF) 1000 44-pin TSOP II 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 c A Min (mm) Max (mm) 1.2 44-pin TSOP II e He A1 A2 b c 0.05 0.95 0.25 1.05 0.45 0.15 (typical) 18.28 10.06 11.56 18.54 10.26 11.96 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 d e He d A2 A1 b e 44-pin SOJ E D l 0-5 A E l 0.80 (typical) 0.40 0.60 E1 E2 Pin 1 B A b Seating Plane A2 E2 c A1 A A1 A2 B b c D E E1 E2 e 44-pin SOJ 400 mil Min Max 0.128 0.148 0.025 1.105 1.115 0.026 0.032 0.015 0.020 0.007 0.013 1.120 1.130 0.370 NOM 0.395 0.405 0.435 0.445 0.050 NOM Package\Access time Plastic SOJ, 400 mil TSOP II, 18.4x10.2 mm NA: not available. Volt/Temp 5V commercial 3.3V commercial 5V commercial 3.3V commercial 12 ns AS7C513-12JC AS7C3513-12JC AS7C513-12TC AS7C3513-12TC 15 ns AS7C513-15JC AS7C3513-15JC AS7C513-15TC AS7C3513-15TC 20 ns AS7C513-20JC AS7C3513-20JC AS7C513-20TC AS7C3513-20TC AS7C SRAM prefix X Voltage:Blank = 5V CMOS 3 = 3.3V CMOS 513 -XX X Package: J = SOJ 400 mil T = TSOP II, 18.4x10.2 mm C Commercial temperature range, 0C to 70 C Device number Access time |
Price & Availability of AS7C3513
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |